The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

May. 09, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Alan Roth, Leander, TX (US);

Eric Soenen, Austin, TX (US);

Russell Kinder, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/14 (2006.01); H02M 1/00 (2006.01); H02M 3/156 (2006.01); H02M 7/42 (2006.01); H02M 3/157 (2006.01);
U.S. Cl.
CPC ...
H02M 1/14 (2013.01); H02M 1/00 (2013.01); H02M 3/156 (2013.01); H02M 3/1584 (2013.01); H02M 3/1588 (2013.01); H02M 7/42 (2013.01); H02M 2001/0003 (2013.01);
Abstract

A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.


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