The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Nov. 30, 2017
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Jae Hyung Jang, Daejeon, KR;

Hee Hwan Ji, Daejeon, KR;

Jin Yeong Son, Daejeon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7835 (2013.01); H01L 21/266 (2013.01); H01L 21/26586 (2013.01); H01L 29/66492 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.


Find Patent Forward Citations

Loading…