The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Mar. 08, 2017
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventors:

Tai-Ju Chen, Tainan, TW;

Yi-Han Ye, Tainan, TW;

Te-Chih Chen, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/148 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66704 (2013.01); H01L 21/02532 (2013.01); H01L 21/28035 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0878 (2013.01); H01L 29/165 (2013.01); H01L 29/407 (2013.01); H01L 29/517 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/66795 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 29/7851 (2013.01);
Abstract

A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.


Find Patent Forward Citations

Loading…