The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Aug. 30, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Hiroaki Katou, Ishikawa, JP;

Syotaro Ono, Ishikawa, JP;

Masahiro Shimura, Ishikawa, JP;

Hideyuki Ura, Ishikawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 29/167 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/4916 (2013.01); H01L 29/7396 (2013.01); H01L 29/7802 (2013.01);
Abstract

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on a part of the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, agate electrode, a first electrode, and a conductive portion. The gate electrode is provided on another part of the second semiconductor region via a gate insulating portion. The first electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region. The conductive portion is provided on another part of the first semiconductor region via a first insulating portion and electrically connected to the first electrode, and includes a portion arranged side by side with the gate electrode in a second direction perpendicular to a first direction from the first semiconductor region to the first electrode.


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