The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Jul. 13, 2017
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chun-Hsiao Li, Hsinchu County, TW;

Wei-Ren Chen, Pingtung County, TW;

Wein-Town Sun, Taoyuan, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01); H01L 29/78 (2006.01); H01L 27/11524 (2017.01); G11C 16/12 (2006.01); H01L 21/326 (2006.01); H01L 23/528 (2006.01); H01L 27/11526 (2017.01); H01L 27/11548 (2017.01); H01L 29/788 (2006.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); H02M 3/07 (2006.01); G11C 16/04 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); G11C 7/04 (2013.01); G11C 7/109 (2013.01); G11C 7/1084 (2013.01); G11C 16/12 (2013.01); H01L 21/326 (2013.01); H01L 23/528 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 29/0646 (2013.01); H01L 29/0688 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/788 (2013.01); H01L 29/7833 (2013.01); H02M 3/073 (2013.01); G11C 16/0433 (2013.01); H02M 2001/007 (2013.01); H05K 999/99 (2013.01);
Abstract

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.


Find Patent Forward Citations

Li, Chun-Hsiao. (2018). Nonvolatile memory having a shallow junction diffusion region (U.S. Patent No. 10103157). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10103157

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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