The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Apr. 03, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Wei Ting, Taipei, TW;

Kuo-Ching Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10876 (2013.01); H01L 21/265 (2013.01); H01L 21/31051 (2013.01); H01L 21/76895 (2013.01); H01L 21/823437 (2013.01); H01L 21/823487 (2013.01); H01L 27/10823 (2013.01); H01L 29/4236 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.


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