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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10103048 B1

PDFFull Text
Date of Patent:
Oct. 16, 2018

Filed:

Aug. 28, 2014

Dual-layer bonding material process for temporary bonding of microelectronic substrates to carrier substrates

Applicant:

Brewer Science Inc., Rolla, MO (US);

Inventors:

Tony D. Flaim, St. James, MO (US);

Jeremy McCutcheon, Rolla, MO (US);

Assignee:

Brewer Science, Inc., Rolla, MO (US);

Attorney:

Hovey Williams LLP

Primary Examiner:

Mark A Osele

Assistant Examiner:

Nikolas R Harm

Int. Cl.
CPC ...
B32B 38/10 (2006.01); H01L 21/683 (2006.01); B32B 37/14 (2006.01); B32B 37/30 (2006.01); B32B 43/00 (2006.01); B32B 37/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); B32B 37/14 (2013.01); B32B 37/30 (2013.01); B32B 43/006 (2013.01); B32B 38/10 (2013.01); B32B 2037/243 (2013.01); B32B 2309/02 (2013.01); B32B 2309/04 (2013.01); B32B 2309/12 (2013.01); B32B 2457/14 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2221/68386 (2013.01); Y10T 156/11 (2015.01); Y10T 156/1168 (2015.01); Y10T 156/1179 (2015.01); Y10T 156/1195 (2015.01); Y10T 156/19 (2015.01); Y10T 156/1961 (2015.01); Y10T 156/1978 (2015.01); Y10T 156/1983 (2015.01); Y10T 156/1994 (2015.01); Y10T 428/1452 (2015.01); Y10T 428/31645 (2015.04); Y10T 428/31667 (2015.04); Y10T 428/31692 (2015.04);
Abstract

A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between the two layers under low-force conditions at room temperature. Optionally, a third layer is included at the interface between the two layers of polymeric bonding material to facilitate the debonding at this interface. This process can potentially improve bond line stability during backside processing of temporarily bonded wafers, simplify the preparation of bonded wafers by eliminating the need for specialized release layers, and reduce wafer cleaning time and chemical consumption after debonding.

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