The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Dec. 19, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Zhibiao Zhou, Singapore, SG;

Chen-Bin Lin, Taipei, TW;

Chi-Fa Ku, Kaohsiung, TW;

Shao-Hui Wu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/786 (2006.01); G11C 14/00 (2006.01); H01L 49/02 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0009 (2013.01); G11C 14/0027 (2013.01); H01L 27/1085 (2013.01); H01L 27/1225 (2013.01); H01L 28/60 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02194 (2013.01); H01L 27/10808 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01);
Abstract

A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.


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