The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Feb. 09, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mahesh A. Iyer, Fremont, CA (US);

Yi Peng, Newark, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3172 (2013.01); G01R 31/3177 (2013.01); G01R 31/31705 (2013.01); G01R 31/31726 (2013.01);
Abstract

An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via multiple logic signals. The JTAG system includes a JTAG interface receives the multiple logic signals. The JTAG system also includes a JTAG hub instantiated in the first partition and being communicatively coupled to the JTAG interface. The JTAG system further includes JTAG-based logic instantiated in the second partition. The integrated circuit device further includes an interface instantiated in the first partition configured to communicatively couple the JTAG hub to the JTAG-based logic.


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