The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Apr. 24, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Takeshi Oshita, Tokyo, JP;

Takanori Hirota, Tokyo, JP;

Masato Suzuki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); H03L 7/081 (2006.01); G11C 11/4076 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0812 (2013.01); G11C 11/4076 (2013.01); H03K 3/037 (2013.01);
Abstract

A delay time is set only within the variable delay time of a clock driver and cannot be set longer than the variable delay time of the clock driver. A control circuit adjusts the delay amount of a variable delay circuit so as to synchronize a pulse phase after a first pulse outputted from a pulse generation circuit passes through the variable delay circuit N times and a second pulse outputted from the pulse generation circuit.


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