The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Sep. 20, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Olivier Vincent Doare, La Salvetat St Gilles, FR;

Didier Salle, Toulouse, FR;

Birama Goumballa, Larra, FR;

Cristian Pavao Moreira, Frouzins, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H03L 7/091 (2006.01); H03L 1/00 (2006.01); H03L 7/095 (2006.01); G01S 7/35 (2006.01);
U.S. Cl.
CPC ...
H03L 1/00 (2013.01); G01S 7/35 (2013.01); H03L 7/091 (2013.01); H03L 7/095 (2013.01); H03L 7/0992 (2013.01); H03L 2207/50 (2013.01);
Abstract

A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal. A digital synthesizer circuit sensor is configured to sense an operational condition of the digital synthesizer circuit and select one of the multiple selectable delays output from the TDC in response to the sensed operational condition. A re-timer circuit is coupled to the digital synthesizer circuit sensor and configured to synchronize the selected delayed DCO output signal with the reference frequency signal.


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