The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2018
Filed:
Sep. 04, 2017
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Anirban Basu, Elmsford, NY (US);
Bahman Hekmatshoartabari, White Plains, NY (US);
Davood Shahrjerdi, White Plains, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/267 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 21/308 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/10 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0243 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02576 (2013.01); H01L 21/26506 (2013.01); H01L 21/26586 (2013.01); H01L 21/28255 (2013.01); H01L 21/308 (2013.01); H01L 21/3085 (2013.01); H01L 21/30604 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/1041 (2013.01); H01L 29/267 (2013.01); H01L 29/66477 (2013.01); H01L 29/66977 (2013.01); H01L 29/7391 (2013.01); H01L 21/30608 (2013.01);
Abstract
Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.