The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2018
Filed:
Jul. 06, 2017
Ki-woong Kim, Seoul, KR;
Hyo-jung Kim, Hwaseong-si, KR;
Kieun Seo, Suwon-si, KR;
Ki Hoon Jang, Hwaseong-si, KR;
Byoungho Kwon, Hwaseong-si, KR;
Boun Yoon, Seoul, KR;
Ki-Woong Kim, Seoul, KR;
Hyo-Jung Kim, Hwaseong-si, KR;
Kieun Seo, Suwon-si, KR;
Ki Hoon Jang, Hwaseong-si, KR;
Byoungho Kwon, Hwaseong-si, KR;
Boun Yoon, Seoul, KR;
Abstract
A method of fabricating a three-dimensional semiconductor device is provided. The method includes providing a substrate with a peripheral circuit region and a cell array region; forming a peripheral structure on the peripheral circuit region, and forming an electrode structure on the cell array region. The electrode structure includes a lower electrode, a lower insulating planarized layer on the lower electrode, and upper electrodes and upper insulating layers vertically and alternatingly stacked on the lower insulating planarized layer, and the lower insulating planarized layer may be extended to cover the peripheral structure on the peripheral circuit region. An upper insulating planarized layer is formed to cover the electrode structure and the lower insulating planarized layer on the peripheral circuit region.