The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2018
Filed:
Sep. 14, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sri Sai Sivakumar Vegunta, Boise, ID (US);
Gowrisankar Damarla, Boise, ID (US);
Jian Zhou, Boise, ID (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); G06F 3/06 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/00 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/7682 (2013.01); H01L 21/76802 (2013.01); H01L 21/76837 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01);
Abstract
A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.