The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Mar. 15, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Shyue Seng Jason Tan, Singapore, SG;

Kiok Boone Elgin Quek, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/105 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); H01L 21/84 (2013.01); H01L 27/0629 (2013.01); H01L 27/1203 (2013.01); H01L 29/42328 (2013.01); H01L 29/42356 (2013.01); H01L 29/66825 (2013.01); H01L 29/7838 (2013.01); H01L 29/7883 (2013.01);
Abstract

Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.


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