The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Sep. 28, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Francesc Cesc Guim Bernat, Barcelona, ES;

Kshitij A. Doshi, Chandler, AZ (US);

Steen Larsen, Portland, OR (US);

Mark A Schmisseur, Phoenix, AZ (US);

Raj K. Ramanujan, Federal Way, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/657 (2013.01);
Abstract

Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.


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