The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2018

Filed:

Aug. 04, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wei Wu, Portland, OR (US);

Yi Zou, Portland, OR (US);

Jawad B. Khan, Cornelius, OR (US);

Xin Guo, San Jose, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/0644 (2013.01); G06F 3/0688 (2013.01); G06F 12/1009 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7201 (2013.01);
Abstract

Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group.


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