Cost-free mtp memory structure with reduced terminal voltages

Abstract

Device and methods for forming a single transistor non-volatile (NV) multi-time programmable (MTP) memory cell are disclosed. The disclosed memory cell is derived via the disclosed method that includes providing a substrate and forming at least a transistor well with a second polarity type dopant and first and second capacitor wells with a first polarity type dopant in the substrate. The method also includes forming a transistor having a floating gate over the transistor well, a control gate over the first capacitor well and coupled to the floating gate, an erase gate over the second capacitor well and coupled to the floating gate. The control gate comprises a control capacitor while the erase gate comprises an erase capacitor that is decoupled from the control capacitor.