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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10090192 B1

PDFFull Text
Date of Patent:
Oct. 02, 2018

Filed:

Nov. 09, 2015

Method for producing a conductor line

Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Matthias Stecher, Munich, DE;

Markus Menath, Regensburg, DE;

Andreas Zankl, Wiesent, DE;

Anja Reitmeier, Regensburg, DE;

Assignee:

INFINEON TECHNOLOGIES AUSTRIA AG, Villach, AT;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Robert Huber

Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/322 (2006.01); H01L 21/74 (2006.01); H01L 21/3115 (2006.01); H01L 21/44 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76804 (2013.01); H01L 21/311 (2013.01); H01L 21/3115 (2013.01); H01L 21/31144 (2013.01); H01L 21/322 (2013.01); H01L 21/44 (2013.01); H01L 21/743 (2013.01); H01L 21/76802 (2013.01); H01L 23/5222 (2013.01); H01L 23/5225 (2013.01); H01L 23/5227 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

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