The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Aug. 30, 2016
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Xing Gu, Allen, TX (US);

Jinqiao Xie, Allen, TX (US);

Edward A. Beam, III, Plano, TX (US);

Cathy Lee, Plano, TX (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4882 (2013.01); H01L 23/3732 (2013.01); H01L 23/3735 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01); H01L 23/3731 (2013.01);
Abstract

The present disclosure relates to a process of forming a semiconductor device with a high thermal conductivity substrate. According to an exemplary process, a semiconductor precursor including a substrate structure, a buffer structure over the substrate structure, and a channel structure over the buffer structure is provided. The channel structure has a first channel surface and a second channel surface, which is opposite the first channel surface, adjacent to the buffer structure, and has a first polarity. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first channel surface. A heat sink carrier is then provided over the high thermal conductivity substrate. Next, the substrate structure and the buffer structure are removed to provide a thermally enhanced semiconductor device with an exposed surface, which has the first polarity.


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