The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Jan. 03, 2018
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Qiyang He, Shanghai, CN;

Chenglong Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/225 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2257 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32134 (2013.01); H01L 21/76816 (2013.01); H01L 21/76897 (2013.01); H01L 21/76895 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.


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