The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2018
Filed:
Mar. 24, 2014
Intel Corporation, Santa Clara, CA (US);
Thiam Wah Loh, Singapore, SG;
Gautham N. Chinya, Hillsboro, OR (US);
Per Hammarlund, Hillsboro, OR (US);
Reza Fortas, Villeneuve Loubet, FR;
Hong Wang, Santa Clara, CA (US);
Huajin Sun, Xi'an, Shaanxi, CN;
Thiam Wah Loh, Singapore, SG;
Gautham N. Chinya, Hillsboro, OR (US);
Per Hammarlund, Hillsboro, OR (US);
Reza Fortas, Villeneuve Loubet, FR;
Hong Wang, Santa Clara, CA (US);
Huajin Sun, Xi'an, CN;
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.