The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Oren Ben-Kiki, Tel-Aviv, IL;

Ilan Pardo, Ramat-Hasharon, IL;

Robert Valentine, Kiryat Tivon, IL;

Eliezer Weissmann, Haifa, IL;

Dror Markovich, Tel Aviv, IL;

Yuval Yosef, Hadera, IL;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 9/30 (2006.01); G06F 11/07 (2006.01); G06F 9/54 (2006.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3802 (2013.01); G06F 9/3004 (2013.01); G06F 9/3016 (2013.01); G06F 9/30043 (2013.01); G06F 9/30076 (2013.01); G06F 9/30101 (2013.01); G06F 9/30145 (2013.01); G06F 9/384 (2013.01); G06F 9/3877 (2013.01); G06F 9/3879 (2013.01); G06F 9/3881 (2013.01); G06F 9/54 (2013.01); G06F 11/0721 (2013.01); G06F 11/0724 (2013.01); G06F 11/0772 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01);
Abstract

An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a processor includes a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among two or more of the SMT cores; and at least one of the SMT cores including at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit, a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit to communicatively couple one or more of the SMT cores to an accelerator device and a memory access circuit to identify an accelerator context save/restore region in a memory responsive to a context save/restore value, the accelerator context save/restore region to share an accelerator context state.


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