The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Dec. 07, 2016
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Ming-Yin Lee, Hsinchu, TW;

Wen-Tsung Huang, Changhua County, TW;

Shih-Yu Wang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H03K 17/687 (2006.01); H01L 27/092 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6872 (2013.01); H01L 27/0266 (2013.01); H01L 27/0629 (2013.01); H01L 27/0928 (2013.01);
Abstract

A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.


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