The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Feb. 21, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ying-Yan Chen, Hsinchu, TW;

Jui-Yao Lai, Changhwa, TW;

Sai-Hooi Yeong, Zhubei, TW;

Yen-Ming Chen, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/167 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01); H01L 21/74 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/743 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/167 (2013.01); H01L 29/456 (2013.01); H01L 29/517 (2013.01); H01L 29/785 (2013.01);
Abstract

A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.


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