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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10083906 B1

PDFFull Text
Date of Patent:
Sep. 25, 2018

Filed:

Feb. 13, 2018

Memory device with buried word line for reduced gate-induced drain leakage current and method for manufacturing the same

Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Kai Jen, Taichung, TW;

Wei-Che Chang, Taichung, TW;

Kazutaka Manabe, Taichung, TW;

Kazuaki Takesako, Taichung, TW;

Noriaki Ikeda, Taichung, TW;

Yoshinori Tanaka, Taichung, TW;

Assignee:

WINBOND ELECTRONICS CORP., Taichung, TW;

Attorney:

Muncy, Geissler, Olds & Lowe, P.C.

Primary Examiner:

Andrew Q Tran

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/5222 (2013.01); H01L 23/5228 (2013.01); H01L 27/10891 (2013.01);
Abstract

A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.

Find Patent Forward Citations

Jen, Kai. (2018). Memory device with buried word line for reduced gate-induced drain leakage current and method for manufacturing the same (U.S. Patent No. 10083906). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10083906

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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