The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Oct. 20, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Richard S. Graf, Gray, ME (US);

Sebastian T. Ventrone, South Burlington, VT (US);

Ezra D. B. Hall, Richmond, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/38 (2006.01); H01L 27/108 (2006.01); H01L 23/34 (2006.01); H01L 25/16 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 23/367 (2006.01); H01L 35/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/38 (2013.01); H01L 23/345 (2013.01); H01L 23/3675 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 25/16 (2013.01); H01L 27/10897 (2013.01); H01L 35/10 (2013.01);
Abstract

An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.


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