Vertical field effect transistors including two-tier select gates and method of making the same

Abstract

A two-dimensional array of vertical field effect transistors is provided, which includes a first-tier structure and a second-tier structure. The first-tier structure includes a laterally alternating sequence of semiconductor rail structures and first dielectric isolation rails that alternates along a first horizontal direction. A first gate dielectric and a first gate electrode that laterally extend along a second horizontal direction are disposed between each neighboring pair of a semiconductor rail structure and a first dielectric isolation rail. The second-tier structure includes a laterally alternating sequence of composite rail structures and second dielectric isolation rails that alternates along the second horizontal direction. Each of the composite rail structures includes a laterally alternating plurality of semiconductor pillar structures and dielectric pillar structures. A second gate dielectric and a second gate electrode are disposed between each neighboring pair of a composite rail structure and a second dielectric isolation rail.