The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Aug. 23, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yun-Yu Hsieh, Hsinchu, TW;

Jeng Chang Her, Tainan, TW;

Cha-Hsin Chao, Taipei, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Li-Te Hsu, Tainan County, TW;

Ying Ting Hsia, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/32134 (2013.01); H01L 21/76879 (2013.01); H01L 21/76886 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.


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