The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Sep. 30, 2016
Applicant:

Shanghai Huali Microelectronics Corporation, Shanghai, CN;

Inventors:

Yun Cao, Shanghai, CN;

Huan Kan, Shanghai, CN;

Fang Wei, Shanghai, CN;

Jun Zhu, Shanghai, CN;

Yukun Lv, Shanghai, CN;

Xusheng Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
G06F 17/504 (2013.01); H01L 21/76819 (2013.01); G06F 2217/16 (2013.01);
Abstract

A simulation method of CMP process comprises: building a CMP model, and forming a matrix table of line width logarithm-density according to the CMP model, and making each intersection of the matrix table correspond to each CMP result under the corresponding line width and density; dividing a layout into a plurality of grids, and converting the equivalent line width and density of each grid into the coordinate of line width logarithm-density in the matrix table; fitting and calculating preliminary CMP simulation results of each grid according to the coordinate of each grid in the matrix table and the CMP simulation results of its adjacent intersections of the matrix table; fitting and computing final CMP simulation results of each grid according to a related weighting factor which considers the impact of adjacent grids for the current grid on the layout; outputting the final CMP simulation results of the whole layout.


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