The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Dec. 18, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wei Wu, Portland, OR (US);

Shigeki Tomishima, Portland, OR (US);

Shih-Lien L. Lu, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/1668 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/06 (2013.01); G11C 7/1048 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 2207/105 (2013.01); G11C 2207/107 (2013.01);
Abstract

Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.


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