The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Mar. 09, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Hai Feng Yang, Shanghai, CN;

Hua Tang, Shanghai, CN;

Fei Liu, Shanghai, CN;

Ben Peng Xun, Shanghai, CN;

Xiao Ming Zhu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/46 (2006.01); H03M 1/06 (2006.01); H03M 1/38 (2006.01);
U.S. Cl.
CPC ...
H03M 1/466 (2013.01); H03M 1/069 (2013.01); H03M 1/38 (2013.01); H03M 1/462 (2013.01); H03M 1/468 (2013.01);
Abstract

A comparator and a successive approximation analog-to-digital converter are provided. The comparator includes a pre-operational amplifier, a latch, a level shift unit, and a reset unit. The pre-operational amplifier receives a to-be-compared signal, and outputs a first-stage amplification signal and a latch clock signal. The latch includes a first inverter circuit and a second inverter circuit, receives and compares the first-stage amplification signal, and outputs a comparison result signal. The level shift unit includes a first level shift circuit and a second level shift circuit, and generates a potential difference between working transistors in the first inverter circuit and the second inverter circuit, respectively. The reset unit includes a first reset circuit and a second reset circuit, and resets a voltage of a node where the level shift unit, the first inverter circuit and the second inverter circuit are coupled when the latch clock signal is at a low level.


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