The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

Jun. 28, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Alexei Sadovnikov, Sunnyvale, CA (US);

Doug Weiser, Plano, TX (US);

Mattias Erik Dahlstrom, Los Altos, CA (US);

Joel Martin Halbert, Tucson, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 23/535 (2006.01); H01L 29/808 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66916 (2013.01); H01L 21/265 (2013.01); H01L 21/324 (2013.01); H01L 23/535 (2013.01); H01L 29/8086 (2013.01);
Abstract

A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.


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