Memory device containing wrap gate vertical select transistors and method of making thereof

Abstract

A gate dielectric layer and a gate electrode layer are formed around semiconductor pillars. The gate electrode layer is patterned to remove top portions that protrude above the semiconductor pillars and divided into multiple strips. Each strip constitutes a gate electrode line including a horizontal layer portion and a plurality of surrounding portions that entirely laterally surround respective channel regions of the semiconductor pillars to form wrap gate vertical select field effect transistors. Vertical stacks of memory elements and alternating layer stacks including a vertically alternating sequence of insulating strips and electrically conductive word line strips are formed above the vertical field effect transistors. Vertical bit lines can be formed inside the vertical stacks of memory elements.