Processor with instruction cache that performs zero clock retires

Abstract

A method of retiring cache lines from a response buffer array to an icache array of a processor including providing sequential addresses to the icache array and to a response buffer array during successive clock cycles, detecting a first address hitting the response buffer array during a first clock cycle, during a second clock cycle that follows the first clock cycle, performing a first zero clock retire to write a first cache line from the response buffer array to the icache array, and during the second clock cycle, bypassing a second address which is one of the sequential addresses. The second address is bypassed given the assumption that it will likely hit the response buffer array in a subsequent cycle. If the second address missed the response buffer array, the bypassed address is replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.