The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2018
Filed:
Aug. 28, 2017
Toshiba Memory Corporation, Tokyo, JP;
Kazuyuki Higashi, Yokohama Kanagawa, JP;
Kazumichi Tsumura, Shinagawa Tokyo, JP;
Ryota Katsumata, Yokkaichi Mie, JP;
Fumitaka Arai, Yokkaichi Mie, JP;
Toshiba Memory Corporation, Tokyo, JP;
Abstract
A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.