The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jan. 09, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Chun Ge, Fremont, CA (US);

Yanli Zhang, San Jose, CA (US);

Johann Alsmeier, San Jose, CA (US);

Fabo Yu, San Ramon, CA (US);

Jixin Yu, Milpitas, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11529 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01);
Abstract

After formation of an alternating stack of insulating layers and sacrificial material layers, a memory opening can be formed through the alternating stack, which is subsequently filled with a columnar semiconductor pedestal portion and a memory stack structure. Breakage of the columnar semiconductor pedestal portion under mechanical stress can be avoided by growing a laterally protruding semiconductor portion by selective deposition of a semiconductor material after removal of the sacrificial material layers to form backside recesses. At least an outer portion of the laterally protruding semiconductor portion can be oxidized to form a tubular semiconductor oxide spacer. Electrically conductive layers can be formed in the backside recesses to provide word lines for a three-dimensional memory device.


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