The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jun. 13, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Masaaki Shinohara, Tokyo, JP;

Shigeo Tokumitsu, Ibaraki, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/764 (2006.01); H01L 21/762 (2006.01); H01L 27/11526 (2017.01); H01L 21/311 (2006.01); H01L 21/308 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 27/11546 (2017.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/764 (2013.01); H01L 21/3083 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 27/11526 (2013.01); H01L 29/66659 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 21/823481 (2013.01); H01L 21/823814 (2013.01); H01L 27/11546 (2013.01); H01L 29/0653 (2013.01); H01L 29/0878 (2013.01); H01L 29/1045 (2013.01); H01L 29/1083 (2013.01); H01L 29/7833 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.


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