The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

May. 12, 2015
Applicants:

Vincent Aubineau, Areches, FR;

Eric Eugene Bernard Depons, Saint Leger en Yvelines, FR;

Michael Andreas Staudenmaier, Munich, DE;

Inventors:

Vincent Aubineau, Areches, FR;

Eric Eugene Bernard Depons, Saint Leger en Yvelines, FR;

Michael Andreas Staudenmaier, Munich, DE;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/39 (2006.01); G06T 1/60 (2006.01); G06F 5/06 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06T 1/60 (2013.01); G06F 5/065 (2013.01); G06F 13/1673 (2013.01); G06F 13/404 (2013.01); G06F 13/4282 (2013.01); G06F 2205/067 (2013.01);
Abstract

A display controller comprises a plurality of channels for fetching data from a memory, a plurality of buffers coupled to the channels for receiving the fetched data from the channels, a buffer controller for controlling the buffers and the channels, and a processing unit coupled to the buffers, the display and buffer controller for receiving the data from the buffers, outputting a control signal to the display based on the received data, and controlling the buffer controller, respectively. Each buffer has a respective fixed memory capacity for storing the fetched data. The processing unit activates layers in the output image for displaying an output image on the display. The channels correspond to associated layers. The buffer controller adds to the respective fixed memory capacity of a particular buffer associated to an activated layer, one further fixed memory capacity of at least one further buffer associated to an inactive layer.


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