Clock tree synthesis based on computing critical clock latency probabilities

Abstract

Systems and techniques are described for context aware clock tree synthesis (CTS). A probability value can be computed for each clock sink in the set of clock sinks, wherein each probability value represents a probability that the corresponding clock sink has a critical clock latency. Next, the set of clock sinks can be clustered into a set of clock sink clusters based on the probability values. An optimization goal for each clock sink cluster can be selected, and an optimized subtree can be constructed for each clock sink cluster based on the selected optimization goal. The synthesized clock tree can be obtained by combining the optimized subtrees.