Gate length upsizing for low leakage standard cells

Abstract

This disclosure describes a library optimization system that creates modified standard cells with reduced leakage currents that meet predefined cell area, timing, and leakage requirements. The library optimization system selects transistors to upsize based upon the fact that transistors of a same type, such as p-channel or n-channel transistors, that are connected in series produce a small reverse bias between the gate and source, known as a stacking effect. The stacking effect results in an inherent decrease in leakage current for the series-connected transistor chain. As such, the library optimization system adjusts gate lengths of transistors that are not part of the transistor series chains having a relatively large amount of same type transistors.