The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2018
Filed:
Dec. 01, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Chaitanya Sreerama, Santa Clara, CA (US);
Stephen H. Hall, Santa Clara, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4282 (2013.01); G06F 13/4022 (2013.01); G06F 13/4234 (2013.01); G06F 15/7817 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract
A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.