The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2018
Filed:
Sep. 29, 2016
Applicant:
Via Alliance Semiconductor Co., Ltd., Shanghai, CN;
Inventors:
Douglas R. Reed, Austin, TX (US);
Rodney E. Hooker, Austin, TX (US);
Assignee:
VIA ALLIANCE SEMICONDUCTOR CO., LTD., Shanghai, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/128 (2016.01); G06F 1/32 (2006.01); G06F 12/0864 (2016.01); G06F 12/0862 (2016.01); G06F 12/0804 (2016.01); G06F 12/0846 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0864 (2013.01); G06F 12/0862 (2013.01); G06F 12/128 (2013.01); G06F 1/32 (2013.01); G06F 12/0804 (2013.01); G06F 12/0846 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/601 (2013.01); G06F 2212/602 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/69 (2013.01); Y02D 10/13 (2018.01);
Abstract
A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for each group of the P groups, monitors a utilization trend of the group and dynamically causes power to be provided to a different number of ways of the N ways of the group during different time instances based on the utilization trend.