The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Apr. 01, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher B. Wilerkson, Portland, OR (US);

Ren Wang, Portland, OR (US);

Antoine Kaufmann, Hillsboro, OR (US);

Anil Vasudevan, Portland, OR (US);

Robert G. Blankenship, Tacoma, WA (US);

Venkata Krishnan, Ashland, MA (US);

Tsung-Yuan C. Tai, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/0891 (2016.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0808 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0891 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/602 (2013.01); G06F 2212/6022 (2013.01); G06F 2212/6028 (2013.01);
Abstract

An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.


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