Circuit for compensating for both on and off-chip variations

Abstract

A system-on-chip (SOC) includes a compensation circuit that compensates for PVT variations of the SoC and an external memory connected to the SOC. The compensation circuit includes first through third delay calculators, first through third delay circuits, first through third latches, first and second comparators, and a delay control circuit. The delay calculators generate first through third delay count data. The delay circuits use three delay counts to generate first through third clock signals. The latches receive data stored in the external memory, and output start-point, mid-point, and end-point data, respectively. The first and second comparators generate increment or decrement signals based on the start-point, mid-point and end-point data comparisons. The delay control circuit generates modified first delay count data, which along with the first through third delay count data, compensate for the PVT variations of the SoC and the external memory.