The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Aug. 06, 2013
Applicants:

Huaxiang Yin, Beijing, CN;

Xiaolong MA, Beijing, CN;

Weijia Xu, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Huilong Zhu, Poughkeepsie, NY (US);

Inventors:

Huaxiang Yin, Beijing, CN;

Xiaolong Ma, Beijing, CN;

Weijia Xu, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/0673 (2013.01); H01L 29/42384 (2013.01); H01L 29/66439 (2013.01); H01L 29/78696 (2013.01);
Abstract

A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.


Find Patent Forward Citations

Yin, Huaxiang. (2018). Method of manufacturing mos transistor with stack of cascaded nanowires (U.S. Patent No. 10068990). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10068990

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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