The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Oct. 27, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chien-Wei Chiu, Beigang Township, TW;

Shin-Cheng Lin, Tainan, TW;

Yung-Hao Lin, Jhunan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66462 (2013.01); H01L 29/0642 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/7788 (2013.01); H01L 29/7827 (2013.01);
Abstract

Embodiments of the disclosure relate to an enhanced-mode high electron mobility transistor. The enhanced-mode high electron mobility transistor includes a substrate, a first III-V semiconductor layer disposed on the substrate, a second III-V semiconductor layer disposed on the first III-V semiconductor layer, a third III-V semiconductor layer disposed on the second III-V semiconductor layer, an amorphous region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first III-V semiconductor layer to serve as an isolation region, and a gate electrode disposed in the amorphous region. The second III-V semiconductor layer and the third III-V semiconductor layer include different materials to form a heterojunction.


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