The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Jun. 16, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Priyanka Pande, Ann Arbor, MI (US);

Cary L. Pint, Nashville, TN (US);

Yang Liu, Santa Clara, CA (US);

Wei Jin, Sunnyvale, CA (US);

Charles Holzwarth, San Jose, CA (US);

Donald Gardner, Los Altos, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D 5/12 (2006.01); H01G 11/84 (2013.01); H01G 11/04 (2013.01); H01G 11/22 (2013.01); C23F 1/02 (2006.01); G03F 7/20 (2006.01); G03F 7/32 (2006.01); H01M 12/00 (2006.01);
U.S. Cl.
CPC ...
H01G 11/84 (2013.01); C23F 1/02 (2013.01); G03F 7/20 (2013.01); G03F 7/32 (2013.01); H01G 11/04 (2013.01); H01G 11/22 (2013.01); H01M 12/005 (2013.01); Y02E 60/13 (2013.01); Y10T 29/417 (2015.01);
Abstract

Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a substrate having a plurality of holes disposed in a surface of the substrate, the plurality of holes being configured in an array of multiple rows and an active material for Faradaic energy storage disposed in the plurality of holes to substantially fill the plurality of holes. Other embodiments may be described and/or claimed.


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