The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2018

Filed:

Dec. 18, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jayanth N. Rao, Folsom, CA (US);

Pavan K. Lanka, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06T 1/20 (2006.01); G06F 9/46 (2006.01); H03K 99/00 (2013.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 9/46 (2013.01); G06F 9/5038 (2013.01); H03K 99/00 (2013.01); G06T 2200/28 (2013.01);
Abstract

A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.


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