Processor with instruction cache that performs zero clock retires

Abstract

A method of operating a processor including performing successive read cycles from an instruction cache array and a line buffer array including providing sequential memory addresses, detecting a read hit in the line buffer array, and performing a zero clock retire while performing successive read cycles. The zero clock retire includes switching the instruction cache array from a read cycle to a write cycle for one cycle, selecting a line buffer and providing a cache line stored in the selected line buffer to be stored into the instruction cache array at an address stored in the selected line buffer, and bypassing a sequential memory address being provided to the instruction cache array during the zero clock retire. If the bypassed address missed the line buffer array, the bypassed address may be replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.